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Accelerating Semiconductor Processes Control with Advanced 3D Optical Metrology

In this webinar, we present case studies that address improving yield, identifying root cause failure and driving next generation device development from bare wafer to final packaged device.
This webinar took place on December 17th 2019

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Webinar Overview

Recent advances in 3D Optical Metrology accelerate in-line quality control for both front and back end processes. In this webinar, we present case studies that address improving yield, identifying root cause  failure and driving next generation device development from bare wafer to final packaged device.

We will highlight requirements for advanced telecommunication, compact on-board electronics, and electric vehicles covering metrology needs for denser interconnect networks, finer redistribution layer (RDL), direct wafer to wafer bonding and wafer fan-out packaging.

Front end (FEOL) examples will include:

  • Wafer bin roughness and edge roll-off
  • CMP efficiency full die flatness
  • CD metrology including TSV, deep trench RIE (Bosch process)
  • Epi layer defect quantification in high power devices


Back end (BEOL) and packaging examples will address:

  • Under Bump Metallization (UBM)
  • Recess defect inspection
  • Full die screening for dense interconnect control

Who Should Attend

This 45 minute interactive webinar will include a Q&A session. It will be valuable for Process Engineers, CMP Engineers, Metrology & Quality Engineers, as well as R&D scientists working across semiconductor, micro-electronics, display technology, printed electronics and telecoms industries.

Speaker

Samuel Lesko
Samuel Lesko
Senior Manager for Optical & Tribology Applications | Bruker Nano Surfaces Division